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Acceleration of NAT and Packet Filter in FPGA for 10G Networks
Orsák, Michal ; Kořenek, Jan (referee) ; Viktorin, Jan (advisor)
This thesis deals with the design of a universal hardware acceleration unit for packet filtering in FPGA for 10G networks. Maximum count of rules is greatly increased by the use of external QDR-II memory. Parameters of accelerator are suitable for NAT, packet filtering and lawful interceptions. The platform uses variable number of processing units. One of them controls accelerator by USB port. The rest is used for network processing.
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Laboratory Pulse Power Supply Controlled by Microcontroller
Chytil, Jiří ; Kubíček, Michal (referee) ; Šebesta, Jiří (advisor)
This project deals with design of switching laboratory supply controled by PIC microcontroler. It consist of three modules: control unit and couple of power modules. Each of the modul is controled by PIC18 microcontroler. Device should work autonomicaly or it can be connected with PC via USB. Output paremeters 0-20 V, 0-1 A. The device has been designed with regard to minimal power consumption.
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Implementation of the Network Traffic Filter by Microblaze in FPGA
Viktorin, Jan ; Korček, Pavol (referee) ; Kaštil, Jan (advisor)
The thesis explores the area of hardware acceleration of a software network traffic filter running inside processor MicroBlaze in the FPGA Spartan-3E. The accelerated application is widely used firewall from the Linux Kernel called iptables, more precisely its extension L7-filter. L7-filter performs lookups inside network traffic using regular expressions. Because of its significant influence on the application performance, it has been exchanged with a hardware unit controlled from the Linux Kernel. The performance has been increased more than twice.
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Network Traffic Analysis Using NXP Processor and FPGA
Orsák, Michal ; Vrána, Roman (referee) ; Kořenek, Jan (advisor)
The primary goal of this thesis is to exploit possibilites of aa entirely new hardware based on NXP LS2088 and FPGA. The secondary goal is to create firmware for this processor working out-of-box and perform optimisations of existing software for L7 analysis. This software was deeply bound to a previous hardware platform. The network processor NXP LS2088 contains many hardware accellerators and a virtual reconfigurable network. This thesis exploits all hardware parts of on this platform. Many tweaks and optimizations were performed based on this analysis to achieve maximum efficieny of software for L7 analysis. There were many intensive optimisations like rewriting for the DPDK library and new hardware or hardware synchronization of worker threads of this application. The main result of this thesis is working platform with efficient L7 analysis software which actively uses accelerators in FPGA and NXP network processor. SDK for new platform is also prepared.
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Network Traffic Analysis Using NXP Processor and FPGA
Orsák, Michal ; Vrána, Roman (referee) ; Kořenek, Jan (advisor)
The primary goal of this thesis is to exploit possibilites of aa entirely new hardware based on NXP LS2088 and FPGA. The secondary goal is to create firmware for this processor working out-of-box and perform optimisations of existing software for L7 analysis. This software was deeply bound to a previous hardware platform. The network processor NXP LS2088 contains many hardware accellerators and a virtual reconfigurable network. This thesis exploits all hardware parts of on this platform. Many tweaks and optimizations were performed based on this analysis to achieve maximum efficieny of software for L7 analysis. There were many intensive optimisations like rewriting for the DPDK library and new hardware or hardware synchronization of worker threads of this application. The main result of this thesis is working platform with efficient L7 analysis software which actively uses accelerators in FPGA and NXP network processor. SDK for new platform is also prepared.
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Acceleration of NAT and Packet Filter in FPGA for 10G Networks
Orsák, Michal ; Kořenek, Jan (referee) ; Viktorin, Jan (advisor)
This thesis deals with the design of a universal hardware acceleration unit for packet filtering in FPGA for 10G networks. Maximum count of rules is greatly increased by the use of external QDR-II memory. Parameters of accelerator are suitable for NAT, packet filtering and lawful interceptions. The platform uses variable number of processing units. One of them controls accelerator by USB port. The rest is used for network processing.
|
|
|
Implementation of the Network Traffic Filter by Microblaze in FPGA
Viktorin, Jan ; Korček, Pavol (referee) ; Kaštil, Jan (advisor)
The thesis explores the area of hardware acceleration of a software network traffic filter running inside processor MicroBlaze in the FPGA Spartan-3E. The accelerated application is widely used firewall from the Linux Kernel called iptables, more precisely its extension L7-filter. L7-filter performs lookups inside network traffic using regular expressions. Because of its significant influence on the application performance, it has been exchanged with a hardware unit controlled from the Linux Kernel. The performance has been increased more than twice.
|
|
|
Laboratory Pulse Power Supply Controlled by Microcontroller
Chytil, Jiří ; Kubíček, Michal (referee) ; Šebesta, Jiří (advisor)
This project deals with design of switching laboratory supply controled by PIC microcontroler. It consist of three modules: control unit and couple of power modules. Each of the modul is controled by PIC18 microcontroler. Device should work autonomicaly or it can be connected with PC via USB. Output paremeters 0-20 V, 0-1 A. The device has been designed with regard to minimal power consumption.
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